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| 42 CY29942 2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer Features * * * * * * * * * * 200-MHz clock support 2.5V or 3.3V operation LVCMOS/LVTTL clock input LVCMOS-/LVTTL-compatible inputs 18 clock outputs: drive up to 36 clock lines 200 ps max. output-to-output skew Output Enable control Pin compatible with MPC942C Available in Industrial and Commercial 32-pin LQFP package Description The CY29942 is a low-voltage 200-MHz clock distribution buffer with an LVCMOS or LVTTL compatible input clock. All other control inputs are LVCMOS/LVTTL compatible. The eighteen outputs are 2.5V or 3.3V LVCMOS or LVTTL compatible and can drive 50 series or parallel terminated transmission lines. For series terminated transmission lines, each output can drive one or two traces giving the devices an effective fanout of 1:36. Low output-to-output skews make the CY29942 an ideal clock distribution buffer for nested clock trees in the most demanding of synchronous systems. Block Diagram Pin Configuration VDD VSS 25 24 23 22 21 20 19 18 17 16 Q0 Q1 Q2 Q3 28 Q4 27 32 31 30 29 VDD TCLK OE 18 Q0-Q17 VSS VSS TCLK NC OE NC VDD VDD 1 2 3 4 5 6 7 8 9 26 Q5 CY29942 Q6 Q7 Q8 VDD Q9 Q10 Q11 VSS 10 11 12 13 Q14 14 Q13 Q17 Q16 Q15 Q12 15 Cypress Semiconductor Corporation Document #: 38-07284 Rev. *B * 3901 North First Street * San Jose * CA 95134 * 408-943-2600 Revised December 21, 2002 VDD VSS CY29942 Pin Description[1] Pin 3 5 9, 10, 11, 13, 14, 15, 18, 19, 20, 22, 23, 24, 26, 27, 28, 30, 31, 32 7, 8, 16, 21, 29 1, 2, 12, 17, 25 4, 6 Name TCLK OE Q(17:0) VDD PWR I/O I, PD I, PU O Description External Reference/Test Clock Input Output Enable. When HIGH, all the outputs are enabled. When set LOW, the outputs are at high impedance. Clock Outputs VDD VSS NC 3.3V or 2.5V Power Supply Common Ground No Connection Note: 1. PD = Internal Pull-Down, PU = Internal Pull-up. Document #: 38-07284 Rev. *B Page 2 of 7 CY29942 Maximum Ratings[2] Maximum Input Voltage Relative to VSS: ............. VSS - 0.3V Maximum Input Voltage Relative to VDD:............. VDD + 0.3V Storage Temperature: ................................ -65C to + 150C Operating Temperature: ................................ -40C to +85C Maximum ESD protection ............................................... 2 kV Maximum Power Supply: ................................................5.5V Maximum Input Current: ............................................20 mA This device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, Vin and Vout should be constrained to the range: VSS < (Vin or Vout) < VDD Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDD). DC Parameters: VDD = 3.3V 5% or 2.5V 5%, VDDC = 3.3V 5% or 2.5V 5%, Over the specified temperature range. Parameter VIL VIH IIL IIH VOL VOH IDDQ IDD Description Input Low Voltage Input High Voltage Input Low Current Output Low [3] Conditions Min. VSS 2.0 Typ. Max. 0.8 VDD -200 200 Unit V V A A V V Input High Current[3] Voltage[4] IOL = 20 mA IOH = -20 mA, VDDC = 3.3V IOH = -16 mA, VDDC = 2.5V Quiescent Supply Current Dynamic Supply Current VDD = 3.3V, Outputs @ 150 MHz, CL = 15 pF VDD = 3.3V, Outputs @ 200 MHz, CL = 15 pF VDD = 2.5V, Outputs @ 150 MHz, CL = 15pF VDD = 2.5V, Outputs @ 200 MHz, CL = 15pF 2.4 2.0 5 285 335 200 240 8 10 12 15 4 Output High Voltage[4] 0.5 7 mA mA Zout Cin Output Impedance Input Capacitance VDD = 3.3V VDD = 2.5V 16 20 pF Notes: 2. Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 3. Inputs have pull-up/pull-down resistors that effect input current. 4. Driving series or parallel terminated 50 (or 50 to VDD/2) transmission lines. Document #: 38-07284 Rev. *B Page 3 of 7 CY29942 AC Parameters[5]: VDD = 3.3V 5% or 2.5V 5%, VDDC = 3.3V 5% or 2.5V 5%, Over the specified temperature range Parameter Fmax Tpd FoutDC Tskew Tskew(pp) Tskew(pp) Tr/Tf Description Input Frequency TTL_CLK to Q Delay[6, 7] Output Duty Cycle[6, 7, 8] Output-to-Output Skew[6, 7] Part-to-Part Skew[9] Part-to-Part Skew[10] Output Clocks Rise/Fall Time[6, 7] 0.8V to 2.0V, VDD = 3.3V 0.2 VDD = 3.3V VDD = 2.5V VDD = 3.3V VDD = 2.5V Measured at VDD/2 1.8 2.3 45 3.3 3.8 Conditions Min. Typ. Max. 200 3.8 4.4 55 200 1.0 1.3 600 1.1 ps ns % ps ns Unit MHz ns 0.5V to 1.8V, VDD = 2.5V Notes: 5. Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with loaded outputs. 6. Outputs driving 50 transmission lines. 7. See Figure 1. 8. 50% input duty cycle. 9. Across temperature and voltage ranges, includes output skew. 10. For a specific temperature and voltage, includes output skew. CY29942 DUT Pulse Generator Z = 50 ohm Zo = 50 ohm Zo = 50 ohm RT = 50 ohm RT = 50 ohm VTT VTT Figure 1. LVCMOS_CLK CY29942 Test Reference for VCC = 3.3V and VCC = 2.5V LVCMOS_CLK VCC VCC /2 GND VCC Q VCC /2 tPD GND Figure 2. LVCMOS Propagation Delay (TPD) Test Reference VCC VCC /2 tP T0 GND DC = tP / T0 x 100% Figure 3. Output Duty Cycle (FoutDC) Document #: 38-07284 Rev. *B Page 4 of 7 CY29942 VCC VCC /2 GND VCC VCC /2 tSK(0) GND Figure 4. Output-to-Output Skew tsk(0) Document #: 38-07284 Rev. *B Page 5 of 7 CY29942 Ordering Information Part Number CY29942AI CY29942AIT CY29942AC CY29942ACT Package Type 32 Pin LQFP 32 Pin LQFP - Tape and Reel 32 Pin LQFP 32 Pin LQFP - Tape and Reel Production Flow Industrial, -40C to +85C Industrial, -40C to +85C Commercial, 0C to +70C Commercial, 0C to +70C Package Drawing and Dimensions 32-Lead Thin Plastic Quad Flatpack 7 x 7 x 1.4 mm A32.14 51-85088-*B All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-07284 Rev. *B Page 6 of 7 (c) Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY29942 Revision History Document Title: CY29942 2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer Document Number: 38-07284 REV. ** *A *B ECN NO. 111095 116777 122876 Issue Date 02/07/02 08/14/02 12/21/02 Orig. of Change BRK HWT RBI New data sheet Added a Commercial Temp. Range in the Ordering Information Add power up requirements to maximum rating information. Description of Change Document #: 38-07284 Rev. *B Page 7 of 7 |
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